1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a transistor in a semiconductor device.
2. Discussion of the Related Art
Generally, the higher the degree of integration of a semiconductor device abruptly rises, the thinner a gate oxide layer between a substrate and gate. An electric field between a gate and source/drain junction is raised to generate gate induced drain leakage (GIDL) current The leakage current is induced by the strong electric field appearing between the gate and drain. In order to reduce the leakage current, many methods have been proposed. For instance, a thickness of a gate oxide layer or an oxide layer on a gate sidewall is increased, or a width of a spacer of a gate is increased.
However, drivability of a transistor is lowered in case of increasing the thickness of the oxide layer on the gate sidewall. In case of increasing the width of the spacer, an area of silicide formed in source and drain regions is reduced. Hence, resistance increases and a process margin of a via contact for connecting the source or drain region to an external device is lowered.